1. Field of the Invention
The present invention relates to power saving control of a plurality of dynamic random access memory (DRAM) devices in a memory control circuit that controls the plurality of DRAM devices.
2. Description of the Related Art
Large scale integrations (LSIs) (system-on-chip (SOC)) in recent years are becoming more sophisticated in functionality by mounting an intellectual property (IP) core other than a central processing unit (CPU) on a chip. Moreover, each intellectual property (IP) core attempts to perform data processing in parallel and thus a memory device mounted on a substrate needs to be a fast and large-capacity device. To meet such requirements, a synchronous dynamic random access memory (SDRAM) device is nowadays used as a memory device, but a plurality of fast memory devices such as double-data-rate (DDR)-SDRAM and DDR2-SDRAM (DDR3, DDR4) is used for still faster access.
In such a system, particularly a system based on a battery operation, it is becoming increasingly difficult not to consider power consumption as an entire system so that a reduction in power consumption of, particularly, a DRAM is becoming an important challenge due to the use of many DRAMs.
A technique discussed in Japanese Patent Application Laid-Open No. 10-302460 is known as a solution thereof. According to the technique, power consumption can be reduced by putting the DRAM into a self-refresh mode.
FIG. 4 illustrates the configuration of a conventional memory control circuit. In FIG. 4, a memory control circuit 200 includes a register 201 to provide instructions to put a DRAM (not illustrated) into self-refresh, an access receiving circuit 202 that receives memory access from an external module such as a direct memory access controller (DMAC) (not illustrated), and a command issuing circuit 203 that issues a command to the DRAM in response to a request from the register 201 or the access receiving circuit 202.
FIG. 5 is a timing chart illustrating an operation of the memory control circuit 200 illustrated in FIG. 4, and a case where a DRAM is set from a normal mode to a power saving mode and, then, the power saving mode is canceled to cause the DRAM to perform access will be described with reference to FIG. 5.
The access receiving circuit 202 receives memory access from the DMAC and asserts an access request signal “access” for the command issuing circuit 203 in a normal mode (t2). The command issuing circuit 203 issues a read or write command to the DRAM according to assertion of the signal “access” (t3). The CPU writes “1” into the register 201 and the register 201 asserts a transition request signal “lowp” to the power saving mode to change the mode from the normal mode to the power saving mode (t5). The command issuing circuit 203 issues a command of power saving mode transition to the DRAM according to assertion of the signal “lowp” (t6). The access receiving circuit 202 receives memory access from the DMAC and asserts the access request signal “access” for the command issuing circuit 203 (t9). The register 201 deasserts the signal “lowp” according to assertion of the signal “access” (t10). The command issuing circuit 203 issues a command to cancel the self-refresh to the DRAM according to deassertion of the signal “lowp” (t10). The command issuing circuit 203 holds the assertion of the signal “access” asserted at time t9 and issues a read or write command to the DRAM after waiting until it becomes possible to issue a command after the cancellation of the self-refresh (t13).
The power saving mode is canceled in a conventional memory control circuit according to access by an external DMAC or the like. Thus, if the memory control circuit has a command queue that temporarily holds a plurality of pieces of access, when access to a memory device in the power saving mode is entered in the command queue, the power saving mode of the device to be accessed is canceled. Therefore, power is consumed in a period after the cancellation of the power saving mode until it becomes possible to issue the access even if the memory device can be maintained in the power saving mode, so that the timing of canceling the power saving mode is not optimized.